Multiplying delay locked loop (MDLL) in time-to-digital conversion

This paper presents the use of a multiplying delay locked loop (MDLL) for delay line-based time interval measurement. The structure is introduced together with the theory behind the performance. Measurement results obtained with a MDLL-based time digitizer designed with 0.35 μm CMOS verify the operation and calculated performance of the device. This MDLL technique with modern CMOS technology makes longrange, high-resolution, linear time interval measurement possible with a small, simple one-level interpolation architecture.