A scalable shared buffer ATM switch architecture

A scalable shared buffer switch architecture for asynchronous transfer mode (ATM) with O(/spl radic/N) complexity for memory bandwidth requirement and maximum crosspoint switch size, and O(N) scalability for buffer memory size is proposed. Access time to buffer memories has been reduced by virtue of parallel access. The switch architecture features multiple buffer memories between the input and output side crosspoint switches. The new switch architecture is better than the standard shared buffer approach as it eliminates the use of input and output time division multiplexing and makes it possible to meet buffer memory access time limitations for larger switches. At the same time, the proposed switch architecture is able to keep the crosspoint switches from growing as O(N/sup 2/) as is the case in the pure multibuffer architecture. The proposed architecture offers a good compromise between the simple shared buffer and shared multibuffer architectures Architectural and implementation details are discussed and a quantitative comparison between the buffer architectures given. Implementation of an 8/spl times/8 switch in 1.0 /spl mu/m CMOS technology is described.