Single-Metal Dual-Dielectric (SMDD) gate-first CMOS integration towards low VT and high performance

This paper overviews integration challenges of low-V
_T
gate-first CMOS featuring one metal gate electrode and one host dielectric with Al
₂
O
₃
and La
₂
O
₃
cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low V
_T
enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the art SMDD device results are reported.