Generating an Efficient Instruction Set Simulator from a Complete Property Suite

Instruction set simulators can be used for the early development andtesting of software for a processor before it is manufactured. Whilegate-level simulation of the overall design offers cycle-accurateresults, performance of the simulation is typically not sufficient forin-depth software testing. In addition, such a gate-level simulationcannot be carried out in the early phases of the design process whenonly the instruction set architecture (ISA) is present and the designis not yet complete. Therefore, more abstract simulators are based onthe ISA; these simulators can achieve a performance of several millioninstructions per second. However, by introducing a simulator separatefrom the design, the ISA has to be re-implemented for thesimulator. Therefore, there is a risk that the instruction setsimulator is not in sync with the design or the ISA. We present anapproach to automatically generate an instruction set simulator from acomplete property suite, which can be used for the formal verificationof the processor. In this way, we obtain a provably correct simulatorwith relatively small effort. We show the feasibility of the approachfor an industrial design; the performance of the resulting simulatoris comparable to custom state-of-the-art simulators.