HAL: heuristic algorithms for layout synthesis

This paper describes graph theory based algorithms for layout synthesis of leaf cells. A new layout style termed 1-1/2-d layout style is used for the layouts. The transistors are aligned based on common poly gates or common circuit nodes between two sets of transistors. The two sets of transistors can be a set of PMOS transistors and a set of NMOS transistors, or both the sets can be formed by similar types of transistors. This layout style and the choice of transistor sets provide a unique capability of making efficient use of the layout area for circuits with a large difference in the number of PMOS and NMOS transistors. The algorithms can thus be used to form symbolic layouts for a general class of CMOS circuits, e.g., static dual type of circuitry or static CMOS circuitry with non-dual pullup and pulldown networks and dynamic logic styles (e.g., CPL, Domino, etc.). The algorithms have been implemented in GENIE (Mentor Graphics). In spite of possessing the extra features not usually found in the other algorithms in the literature, these algorithms provide extremely competitive results when compared to the handcrafted layouts and other algorithms in the literature. These algorithms are not only quite flexible in supporting various circuit styles, but are also run time efficient.