Development of high density memory IC package by stacking IC chips

A stacked chip package in which two memory chips are stacked with no increase in package thickness has been developed. The majority of its material composition is nearly identical to that used for conventional TSOP packages. Chips are mounted on the top and bottom sides of a die pad. This arrangement keeps the assembly process from becoming too complex and allows full use of existing manufacturing facilities. Cracking of the passivation was avoided by coating the chip surface with a polyimide film and using a buffer on the jig. Package quality was maintained even if the jig buffer contacted the chip surface with a polyimide during the die and wire bonding processes. The overall package reliability is equivalent to that of conventional TSOPs.