A statistical methodology developed to maximize the return on investment of process capability improvement

A statistical methodology which can be used to maximize the return on investment of process capability improvement is presented. This method is an extension of Quality Engineering by Design (QED) techniques, and incorporates both process simulation techniques and product manufacturing data. The resulting combination provides process engineers and management in manufacturing environment with a useful weapon against variability. The focus is on reducing process variability in order to achieve device performance specifications. A case study is presented on the variation reduction of the nMOS threshold voltage (Vtn) in the RIT CMOS process. The end result is a plan which will determine where variation reduction efforts will be most rewarded, and possible strategies which can be used to achieve the required product quality.