High efficiency synchronous DRAM controller for H.264 HDTV encoder

This paper addresses a high efficiency memory controller of Synchronous DRAM to improve memory bandwidth in H.264/AVC HDTV encoder. The feature of SDRAM and memory access patterns of H.264/AVC encoder are analyzed for suitable controller architecture designing. Based on page breaks analysis of memory access patterns, a new data arrangement in SDRAM has been used to improve bus efficiency in H.264/AVC HDTV encoder by reducing the overhead cycle of page-activation. In addition, in order to reduce the bandwidth requirement, a well-arranged frame buffer is used in proposed SDRAM controller. Experiment results show that the proposed architecture has improved 40% performance of SDRAM bus efficiency.