Design and implementation of list-of-2 Viterbi decoder with VHDL and its application

To use list Viterbi decoding (LVA) as inner decoder with error detection outer codes, the list size must be large enough to almost always include the correct seqeunce. However, if error correction is used, a very short list of two can be enough. Convolutional vector symbol decoding (conv. VSD) has been shown that it could select the correct input sequence from a list of multiple sequences. Previous work showed that list of 2 choice was the most effective size in terms of performance and complexity from the implementation viewpoint of conv. VSD. In addition, list-of-2 Viterbi has been simulated with C++ program to demonstrate that it is suitable as the inner decoder for conv. VSD outer codes for some channels. In this paper, we propose the design and implementation of LVA with list of 2 in a hardware language called VHDL. This VHDL program can readily be implemented on an FPGA board and used as the inner decoder for the conv. VSD. The results show that VHDL program worked exactly as designed by comparing thier outputs with the output of previous C++ program.