Relation between etch pit pairs and pipeline defects in CMOS device

We report for the first time an observed physical relationship between pipeline defects and decorated etch pits. In our implementation of 1 micron EEPROM production, pipeline defect shorting the source to the drain was found to be the major cause of yield loss. Positive correlation was found between the extent of rejects due to pipeline defects and a type of paired decorated etch pit density. SEM analysis identified the etch pit pair to be the ends of a dislocation that passes through areas where pipes are usually found. The density of these paired etch pits was successfully used as an inline tool for isolating the cause of pipeline defects, evaluating fixes, and resolving the problem. The proposed mechanism for the formation of the pipes is interaction between the compressive stresses from surrounding oxide on the island of silicon, plus implant damages resulting in dislocations. The pipe defects were portions of dislocations in a p-channel region that had been doped n-type by phosphorus diffusing in from the source and drain region. The problem was eliminated by combination of a stress relieving anneal and a reduction in the nitride thickness used in the LOCOS process to minimize stress.