Detecting I/sub DDQ/ defective CMOS circuits by depowering

When disconnecting the power supply line of a CMOS circuit in its quiescent state, the capacitances present in the circuit hold the logic valves in all their nodes. In non defective circuits, these capacitances discharge very slowly due to the extremely small I/sub DDQ/ discharge current. On the other hand, in I/sub DDQ/ defective circuits the discharge is faster than in the previous case because the current involved is many orders of magnitude greater. Some time after the discharge starts, the logic state of some nodes may change, and when this change propagates to a primary output, the defect is detected. Experimental work has been performed to prove these effects and to evaluate their fault detection capabilities.