Design of interleaved multithreading for Network Processors on Chip

Thread level parallelism and multi-core processors are current alternatives to increase performance of general-purpose applications. In the same way, networks-on-ohip (NoCs) are the main alternatives for supporting packet throughput for the next generations of many-core processors. NPoC (network processor on chip) is a proposal to increase the performance of programmable NoC routers and multi-cluster NoC architectures using interleaved multithreading (IMT) technique. Therefore, the main goal of this paper is to present the design impact of interleaved multithreading for network processors on chip focusing on area and performance feasibility. Results show that NPoC-based router has an acceptable and similar area relative to a conventional NoC, and higher performance up to 7.1% than the same NPoC version without IMT.