A 10Gb/s wire-line transceiver with half rate period calibration CDR

This paper presents the design of a 10 Gb/s low power wire-line transceiver in 65 nm CMOS process with 1 V supply voltage. The transmitter occupies an area of 430 mum times 240 mum, consumes 50.56 mW power and has a 5-order programmable pre-emphasis equalizer. The receiver occupies an area of 300 mum times 500 mum. With the novel half rate period calibration clock data recovery (CDR) circuit, the receiver consumes only 52 mW power. The receiver combines a low power wideband programmable continuous time linear equalizer (CTLE) and a 3-order decision feedback equalizer (DFE).