Ultra-low power subthreshold flip-flop design

In recent years, low power design has become one of the main focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, where efforts are taken to reduce subthreshold leakage, operation of digital circuits in the subthreshold region, utilizes this current, minimizing power consumption in low-frequency systems. This paper proposes two architectures for implementing flip-flop cells, designed to operate in the subthreshold region. Both cells integrate a gate-diffusion input (GDI) multiplexer in their designs to minimize area and capacitance. Timing parameters of the flip-flops are calculated and techniques for improving the timing characteristics are proposed. The proposed designs are simulated in a standard 90 nm process achieving a power dissipation of 8.4 nW in a typical corner at VDD = 300 mV with a delay of 51.7 nsec.