Simulating "large" microwave circuits with the parallel Planar Generalized Yee algorithm

The Planar Generalized Yee (PGY) algorithm is presented for the full-wave analysis of "electrically-large" grounded co-planar (GCPW) circuits. The method has a significant advantage over traditional Yee-algorithm based finite-difference time domain (FDTD) methods in that it is based upon unstructured and irregular grids. The PGY algorithm has been efficiently implemented on massively parallel computers and is ideal for the rapid, broadband analysis of packaged, large, high-density circuits and multi-chip modules (MCM's). Simulation and measured results on several "electrically-large" circuit structures are presented.