1/4 W optical receiver and clock recovery circuit for Gb/s digital fiberoptic links

Design and simulation of a low power consuming MMIC chip set is presented in this paper, which is used as an optical receiver and clock recovery circuit operating up to 1.25 Gb/s. This design is based on BTA24 Si BJT transistor array from Bipolarics. Major design innovations such as push-pull self-oscillating mixer and a push-push frequency doubler is used to provide a total power consumption of 247 mW in an area of only 700 /spl mu/m/spl times/700 /spl mu/m.