Enable++: a general-purpose L2 trigger processor

Two years of experience with the two prototype FPGA processors Enable-1 and DecPeRLe-1 reveal that field programmable processors are the best choice for realizing a data-driven second level (L2) trigger for ATLAS. This paper presents Enable++, a modular and thus scalable 2nd generation FPGA processor that offers several substantial enhancements to the previous systems: In order to meet the varying demands of all ATLAS subdetectors Enable++ is structured into three different state-of-the-art modules for providing computing power, flexible and high-speed I/O communication and powerful intermodule communication with a raw bandwidth of 3.2 GByte/s by an active backplane. The computing core offers scalable computing power by virtue of a configurable processor topology, a 4/spl times/4 FPGA array and 12 MByte of distributed RAM. For building new applications the system provides a comfortable programming and debugging environment consisting of a compiler for the C-like hardware description language spC, a simulator and a source level debugger for hardware design. The most computing intensive tasks in L2 triggering are the feature extraction algorithms. From experience with Enable-1 we expect that Enable++ surpasses modern RISC processors by a factor of 100 to 1000.