Design impact study of wiring size and barrier metal on device performance toward 22 nm-node featuring EUV lithography

The resistance of wiring with a width of less than 40 nm was firstly evaluated by using an EUV lithography (lambda=13.5 nm). The resistance was quite high in narrow wiring with conventional Ta barrier film, while a very low effective resistivity rho
_eff
of lower than 4.5 muOmega cm was obtained by using PVD-Ru barrier film. This difference was attributed to combination of thinner barrier metal films in the trench, the larger grain size and better filling capability of the Ru barrier metal. The predicted circuit-performance using the Ru barrier was 10% higher than that with Ta barrier and the operating-speed distribution was estimated to be less than 5 % for the 22 nm-node CMOS generation.