Analysis of a control mechanism for a variable speed processor

One limitation on the operating speed of electronic circuits is the rate at which the packaging can dissipate heat. In CMOS technology, the heat generated by a processor is approximately proportional to its clock rate. The paper examines the idea of using a variable speed processor (VSP) that can be operated at a high clock speed, and then slowed down to a lower speed before heat accumulation destroys the circuit. Under a workload consisting of bursts of work alternating with idle periods (corresponding to cache misses or other delays), this results in a higher average operating speed. The paper shows the optimality of a bang bang control for the clock rate. It also examines an easier to implement policy that estimates the junction temperature through an upper bound, and uses this to control the clock rate. Closed form expressions are derived for the mean rate of instructions executed by a VSP using each control method. Numerical studies show that both policies give substantial improvements in performance over a single speed processor. Furthermore, the studies suggest that a VSP with a maximum clock rate of 2-4 times that of the single speed processor would suffice to obtain the bulk of the performance improvement. In many cases, the average throughput gain is on the order of 40-60%, without exceeding thermal limits.