Process integration for the high speed NAND flash memory cell

The high speed NAND flash memory cell with a read access time of 80 ns has been demonstrated. In the process integration of the high speed cell, complementary polycide bit lines with the ground selection scheme, self-aligned field through implantation, and metal source line have been introduced. The reliable high speed NAND cell operation has been achieved by enhanced sensing voltage swing, increased cell current and reduced bit line loading.