A 4 Gsamples/s line-receiver in 0.8 /spl mu/m CMOS

The interconnects between chips are gaining in importance. We study a line-receiver to find out what is the limit of transmission speed onto a CMOS chip. The high tracking-speed of an NMOS sampling switch is used together with parallelism to attain high data-rates. 4 Gsamples/s sample-rate and 2 Gbit/s bit-rate (two samples per bit) has been shown experimentally with a 0.8 /spl mu/m CMOS test-circuit. Single pulse measurements and simulations show that even higher rates are possible.