Underfill delamination to chip sidewall in advanced flip chip packages

A number of failure mechanisms related to the underfill material in flip chip plastic ball grid array packages are well documented in the literature (underfill-to-chip passivation delamination, underfill-to-substrate soldermask delamination, chip cracking, interconnect fatigue, etc.). This paper discusses the delamination of the underfill from the chip sidewalls, another failure mechanism which has become more prevalent with component material changes, increases in die dimensions, finer C4 pitches and substrates with larger coefficient of thermal expansion. A detailed study is presented for the initiation of underfill-to-sidewall delamination, based on experimental data as well as finite element modeling. It is shown generally that both stress at the chip-underfill interface near the chip corner, and poor adhesion of the underfill to the chip sidewalls contribute to the initiation of underfill delaminations. Various parameters influencing stress (package design, underfill material thermo-mechanical properties) and adhesion (underfill base chemistry and additives, filler treatment, chip sidewall cleanliness) are discussed.