Study of interconnection process for fine pitch flip chip

Today, flip chip technology is a main stream of interconnection in microelectronic packaging and market forces continue to drive toward finer pitch interconnections. In this paper, fine pitch flip chip (FPFC) interconnection technology (i.e., less than 60 mum pitch) will be described. Two types of 50 mum pitch bump (Au stud & Cu pillar) will be evaluated and two different flip-chip (FC) bonding methods will be studied. Package structures of bare die flip-chip CSP (chip scale package) and also over molded version will be studied for reliability performance and volume assembly fit. For characterization, structure analysis will be performed at each reliability read point. Finally this paper will conclude by identifying the most robust bonding method for the FPFC devices.