Electrical design and demonstration of an embedded high-pin-count LSI chip package

Design techniques for an ultra-thin LSI package embedding a high-pin-count LSI chip in the thin package substrate have been developed to achieve the excellent electrical performance, as well as low warpage and high heat removal. The embedded chip package we designed is 27 mm by 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against the six metal layers of the product flip chip ball grid array (FCBGA) package using the same chip. Although the two power plane layers have been removed from the substrate, the low impedance of the power distribution network (PDN) is achieved by utilizing many bundles of fine vias. A 0.5-mm-thick copper plate attached to the LSI chip's backside provides the signal return path, and contributes to the flatness of this thin package. It also effectively removes heat from the chip. Our design for a product LSI chip with approximately 1,500 pins demonstrates excellent electrical performance as well as small thickness, low warpage, and a high rate of heat removal. Function tests using an LSI tester and a PC-like system board successfully demonstrate the outstanding performance of the LSI chip.