A multi-channel time-to-digital converter chip for drift chamber readout

A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e. 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using an TDC comprised of a delay locked loop, latch and encoder. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. Eight complete channels of timing and amplitude information are multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are subsequently transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in an 0.8 /spl mu/m triple metal CMOS process. The measured results indicate that the differential non-linearities of the TDC and the FADC are 200 ps and 10 mV, respectively. The integral non-linearities of the TDC and the FADC are 230 ps and 9 mV, respectively.