Fast prototyping of memory models in VHDL for hardware emulation

In this paper, we present a methodology whereby the whole synthesis and prototyping cycle can be speeded up simply by extending the acceptable VHDL subset to include hitherto unsynthesisable constructs. VHDL elaboration transformations as well as some compiler optimisation techniques can be performed to ensure that the VHDL model is still acceptable by commercial synthesis tools. The advantages of this methodology are shown using a real industrial application: the development of a generic VHDL memory model for fast system reconfiguration in a hardware emulation environment.