Quick and Clean: Stencil Lithography for Wafer-Scale Fabrication of Superconducting Tunnel Junctions

This paper presents a resist-less process for parallel fabrication of sub-micrometer Al-AlO
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-Al superconducting tunnel junctions. A custom stencil is fabricated containing 200 nm low-stress SiN membranes with micro-apertures. The stencil is aligned and clamped with a 1 mum accuracy to a substrate wafer containing Ti-Au contact electrodes. The junctions are fabricated by evaporating Al from two different angles, with an intermediate in-situ oxidation step. Measurements of the devices down to 0.3 K show stencil lithography is a good candidate for parallel, resist-less patterning of sub-micrometer area tunnel junctions. Challenges are addressed and further developments are proposed.