Experimental operation of an RS flip-flop composed of nonlatching Josephson gates

We present the experimental implementation of an RS flip-flop (RS-FF) composed of dc-biased coupled-SQUID (C-SQUID) gates. The C-SQUID gate is a combination of a single-junction SQUID and a double-junction SQUID. This gate utilizes nonhysteretic Josephson junctions and it is operated in nonlatching mode with dc-biasing. Several logical functions are able to be realized with a C-SQUID gate by adjusting the input bias and the input signal levels. The speed performance of the gate is evaluated by simulation for ring oscillators, and the minimum switching delay of 6.5 ps/stage is obtained under Josephson critical current density of 10 kA/cm/sup 2/. We have fabricated the RS-FF composed of two C-SQUID NOR gates. The circuit is integrated using a Nb/AlO/sub x//Nb junction technology and its operation is demonstrated experimentally.