Effects of Plasma-Induced Si Recess Structure on n-MOSFET Performance Degradation

Performance degradation of n-MOSFETs with plasma-induced recess structure was investigated. The depth of Si recess (dR) was estimated from the experiments by using Ar gas plasmas. We propose an analytical model by assuming that the damage layer was formed during an offset spacer etch. A linear relationship between threshold voltage shift (DeltaV
_th
) and
d

_R
was found. Device simulations were also performed for n-MOSFETs with various (d
_R
). Both |DeltaV
_th
| and off-state leakage current increased with an increase in
d

_R
. The increase in |DeltaV
_th
| becomes larger for smaller gate length. The results from device simulations are consistent with the analytical model. These findings imply that the Si recess structure induced by plasma damage enhances V
_th
-variability in future devices.