An Architecture for Bitonic Sorting with Optimal VLSI Performnance

We propose a class of designs of a new interconnection network, the pleated cube-connected cycles (PCCC), which can impleement stable bitonic sorting of n records of size q in area A = O(q
²
n
²
/T
²
), where T, the computation time, is in the range [Ω(q log
²
n), O(q √n/(q+ log n))]. Thus, this network is an AT
^2,/R
-optimal bitonic sorter in the synchronous VLSI model of computation under the word-local restriction.