A scalable low power vertical memory

An experimental memory array with the capability of operation at cell area below 0.15 /spl mu/m/sup 2/ for the gigabit generation is described. Channel injection through a thin oxide (/spl sime/3 nm) into the floating gate of a vertical transistor allow scalable, ultra-low power, and dense (4-6 square of the minimum pitch) structures that operate with 100 ns write speeds at low voltages, >10/sup 5/ s retention time, and endurance exceeding 10/sup 10/ cycles with no measurable degradation. Non-volatile structures are achieved with a compromise in speed and power. Multiple-self alignment and use of thin film growth, deposition, and etching techniques allow for a significant reduction in the lithography needs.