Performance and reliability optimization of ultrashort channel CMOS device for giga-bit DRAM applications

Extensive reliability and performance characteristics of ultrashort channel CMOS devices with various process conditions for giga-bit DRAM were investigated. Using conventional process with various oxide thicknesses and doping profiles, we fabricated 0.1 /spl mu/m channel length n/sup +/ gate MOSFETs with excellent electrical characteristics. Based on these results, practical device design windows were proposed for 1.5 V operating bias. Considering significant improvement of hot carrier lifetime of ring-oscillator, hot-carrier reliability is not a major constraint for L/sub eff/=0.1 /spl mu/m at 1.5 V operating bias.