Efficient npn operation in high voltage NMOSFET for ESD robustness

This paper presents a design technique to achieve parasitic npn turn-on in a high voltage drain extended nMOS (DEnMOS) transistor under ESD conditions. Using the gate-coupled design technique, the overlap between the n/sup -/ drain and the gate is designed for optimum gate potential transient corresponding to maximum substrate current generation under ESD, which can subsequently lead to forward biasing of the substrate-source junction. This approach resulted in more than 6 kV of ESD level for a 600/5 /spl mu/m DEnMOS device.