Novel approach using tapers for high power FET chips characterization

This paper introduces a novel approach for the characterization of high power devices of total gate periphery (GP) around 20 mm. Electrical models of two power FET chip devices (GP=4.8 mm and 12.6 mm) are obtained from scattering parameters measurements based on broadband impedance transformers and from DC pulsed measurements. A small scaling factor applied on these electrical models allows one to analyse high power devices.