Low-Cost BISDC Design for Motion Estimation Computing Array

This paper develops a built-in self-detecting/correcting (BISDC) architecture design for motion estimation computing array (MECA). Based on the error-detecting/correcting concepts of low cost remainder and quotient (RQ) arithmetic codes, any error of each processing element (PE) in MECA can be effectively detected and corrected on-line by using the proposed built-in self-detecting (BISD) and built-in self-correcting (BISC) circuits, respectively. Performance analysis and evaluation show the proposed BISDC architecture has little area overhead and timing penalty.