A Novel SET/SEU Hardened Parallel I/O Port

The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event transient SET and single event upset SEU, caused by energetic particles striking system wires and flip flops. This paper presents a novel SET/SEU-detection technique for I/O ports where different sampling times used to detect the effects of SET/SEUs. The power dissipation, area, reliability, and propagation delay of the SET/SEU-detection I/O port are analyzed by HSPICE v.X-2005.v9 simulation. The results show that this I/O port can detect all SET/SEUs, by consumption of about 113% more power and occupation of 145% more area than simple I/O port.