Hardware architecture for H.264/AVC intra 16×16 frame processing

In this paper, we present an efficient H.264 / AVC intra 16times16 frame coder system. The system achieves real-time performance for video conference applications. The INTRA 16times16 is composed by intra 16times16 prediction, integer transform, quantization AC, inverse quantization AC, quantization DC, hadamard, inverse quantization DC, and inverse integer transform. The proposed hardware is implemented in VHDL. The VHDL RTL code works at 160 MHz in an Altera Stratix II FPGA and it code 129 Mpixels per second. This work will be used as an intellectual property (IP) integrated in H.264/AVC encoder.