Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design

Difference between ISSQ and IDDQ testing strategies is presented, discussing the dependency of area overhead and sensing speed on the technology. The current sensor implementation style suitable for cell-based design methodology or semi-custom design style is proposed Experimental results for each strategy are discussed. Finally, different types of partitioning strategies are showed, taken into account the parallelism of the gates.