Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks

In digital circuits, a transistor connected to a particular circuit node does not always load that node by a gate capacitance proportional to C/sub ox/WL if the transistors connected to its source are turned off. Such an observation, illustrated in this paper by a detailed analysis of the Yuan-Svensson D-flip-flop (D-FF) can be used to advantage both in sizing the transistors and in developing better configurations. A glitch-free, general purpose, and faster D-FF is presented here which has complementary outputs and runs at frequencies from tens of hertz to a couple of gigahertz for a 1-/spl mu/m CMOS technology. Measured maximum clock frequency of a divide-by-16 circuit is 2.65 GHz at 5 V supply, whereas that of a dual-modulus frequency prescaler, dividing by 64/65, goes up to 1.6 GHz at 5 V.