Scan more with memory scan test

Almost all manufacturing memory test programs use the time-efficient Scan test to screen the defective chips in an early stage. Usually, Scan is used to screen out the easy-to-detect hard faults like stuck-at-faults. In this paper we will show how Scan can be modified to increase the fault coverage and detect unique faults. It will be shown that many additional faults are detectable using Scan if appropriate read-write sequence, an appropriate data-background and appropriate addressing method are used. Such additional faults consist not only of static/traditional faults, but also of dynamic and time-related faults which are of increasing importance with the technology scaling. Examples of such faults are dynamic faults in the peripheral circuits (e.g., sense amplifiers, pre-recharge circuits, etc) and in the address decoders. Industrial results are presented to validate the proposed approach.