Performance evaluation of MIC@R router for on-chip networks

The paper presents a performance evaluation of MIC@R router for Networks-on-Chip (NoC) design. Its architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. The proposed router architecture is implemented in ASIC technology and evaluated in 2D Mesh networks with four routing schemes: Deterministic, Fully Adaptive (FA), Proximity Congestion Awareness (PCA) and Proximity Hot-Spot Awareness (PHSA). The last scheme is a novel routing technique that improves better the latency and throughput compared to others schemes. The obtained results show that our router, combined with different routing algorithms has efficient performances.