Thermal analysis of integrated circuit devices and packages

The integrated circuit device is modeled as a four-layer structure with multiple heat sources located on the surface of the first layer and with the fourth layer representing the device package. Each layer is assumed to have the same rectangular dimensions. Using the separation of variables, an analytical solution for the temperature at any location inside and on the boundaries of the structure is derived. Based upon the solution obtained, a computer program, Thermal, has been written in Fortran. Characteristics of the solution were studied, and several representative device structures were analyzed. The results of the simulation show how the device thermal resistance is affected by the die-bonding layer properties, the electrodes on the chip surface, and the heat spreader at the bottom surface of the chip. A FET power device was also analyzed to illustrate the very narrow hot zones produced on the chip surface, suggesting that the thermal measurement techniques must have adequate spatial resolution to measure the peak temperatures accurately. The lateral spread of heat flux into the regions of the package extending beyond the chip dimensions was studied using the boundary element method. An iteration technique based on the analytical solution has also been developed to account for the effect of this lateral heat spread. The corrected temperature using this iteration technique agrees to within 3.7% with that obtained using the boundary element method.<
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