A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array

A 622 Mb/s clock recovery PLL for SDH/SONET OC-12 is implemented in a 0.8 /spl mu/m CMOS technology. With time-interleaved phase detection scheme, this PLL performs clock recovery and 1:8 demultiplexing simultaneously. It dissipates 200 mW with a single 5 V supply, whose core occupies 800/spl times/900 /spl mu/m/sup 2/. RMS jitter of the recovered 78 MHz clock is 46 ps (0.36%).