AMD's next generation MACH 3 and 4 family optimized for flexibility, fast speed and predictable routing delay

This paper describes the silicon architecture of AMD's next generation Macro Array CMOS High Speed/High Density (MACH family of PLDs). With an advanced 0.65 /spl mu/m technology and an innovative architecture, the next generation MACH family offers gate density up to 10000+ PLD gates with fixed, predictable worst-case pin-to-pin delays of 15 ns and External systems clock frequency up to 50+ MHz.