Performance driven multiple-source bus synthesis using buffer insertion

A heuristic algorithm for a given topology of a multiple source and multiple sink bus to reduce the signal delay time is proposed. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. Experiments show up to 7.2 %, 20.7 %, and 29.6 % improvement in delay for 2.0, 0.5, and 0.3 micron technologies, respectively.