A built-in self test scheme for VLSI

We present a novel approach for built-in self test (BIST) for VLSI. Many conventional BIST schemes use signatures generated by a linear feedback shift register (LFSR) or a multiple input signature register (MISR) for determining whether the device under test is faulty or fault free. In the approach presented, fault detection is made based on the number of different states the LFSR visits. This number is called the cycle length. It is also shown that such an approach results in the probability of aliasing of 2/sup -(2m-1+m/), where m denotes the number of registers in the LFSR, compared to 2/sup -m/ achieved by conventional signature analyzers. We also present the complexity of the additional hardware required to implement the scheme.