An effective BIST design for PLA

In this paper, we describe a new design of built-in self test for programmable logic arrays (PLAs). The idea is to use a simple deterministic test pattern generator to generate test patterns such that each cross point in the AND array can be evaluated one after another. The simplest multiple input signature register which uses X/sup Q/+1 as its characteristic polynomial is used to evaluate the test results, where Q is the number of outputs. The final signature can be further compressed into only ONE bit. Instead of determining the probability of fault detection only, in this design, the fault detection capability is analyzed using the stuck-at fault, and the contact fault models. It is shown that all these modeled faults can be detected. This design is shown to give a better trade-off between the cost and the performance of built-in self test designs for PLAs.