Test sequence compaction by reduced scan shift and retiming

This paper presents a method to compact test sequences for full scan designed circuits by using the reduced scan shift and the retiming. The reduced scan shift, which we previously proposed, can compact test sequences by omitting unnecessary scan shifts. In this work, retiming, which repositions flip-flops, is introduced to enhance the effect of the reduced scan shift. When the number of flip-flops is reduced by the retiming, the test length is also reduced. Furthermore, this paper shows that the test length can be reduced even when the number of flip-flops is not reduced by the retiming. Under applying the reduced scan shift, the change of the control requirement to flip-flops by the retiming causes the reduction of scan shifts. Test vectors for the retimed circuit can be obtained by modifying the test vectors for the original circuit. Then the computing time to newly generate test vectors can be saved. Finally experimental results are given to show the effectiveness of the proposed method.