Test configurations to enhance the testability of sequential circuits

The majority of design for testability (DFT) methods for sequential circuits are based on scan designs (complete or partial). Nevertheless, with these methods the test application time remains often prohibitive due to the long shift operation to enter the test vector into the scan register. In this paper, we present a DFT method which modifies the circuit in such a way that, during the test operation, several more easily testable configurations are emulated. Different implementations are proposed for these test configurations that are shown to be useful to improve either the controllability or the observability. The efficiency of the method is evaluated in terms of fault coverage, number of modified flip-flops and test application time, using ISCAS89 benchmarks.