Fast summation transformation for battery impedance identification

A battery is an important subsystem for electrical energy storage in many military, space and commercial applications. Consequently, in-situ diagnostics for state-of-health estimation of the battery is also critical for enhancing the overall applications' reliability. Montana Tech, in collaboration with the Idaho National Laboratory (INL) and Qualtech Systems Inc. (QSI), has been working towards the development of advanced techniques for in-situ and real time estimation of a battery's impedance spectrum. INL has shown that the shift of a batteries impedance spectrum strongly correlates to the health of the battery. Two different methods for measurement of the battery impedance spectrum have been developed independently by Montana Tech, NL, and QSI. NL has developed an in-situ system, the Impedance Noise Identification (INI) method of using a random signal excitation to a battery for the purpose of measuring the spectrum of the battery impedance; it is high resolution but not real time. Montana Tech and QSI developed an in-situ system, Compensated Synchronous Detection (CSD) that is very near real time but trades off resolution for speed of measurement. New developments with CSD hold promise of an even faster and more accurate response. A new measurement and data processing technique has been developed, Fast Summation Transformation (FST). The FST technique uses a mathematical uniqueness similar to what was realized with the Fast Fourier Transform (FFT) to enable crosstalk elimination, speed of measurement, and speed of data processing. A prototype hardware system that is compatible with both the INI or CSD algorithms is now under development. Test results are continuously being compared to standardized measurement techniques such as electrochemical impedance spectroscopy. It is expected that the FST algorithm will be fully compatible with this hardware platform. This paper develops the theory of the algorithm and analytically validates it with computer simulations. It also provides preliminary testing results of the FST implementation on the CSD hardware platform.